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Product Description
Sirenza Microdevices' XD010-12S-D4F 15W power module is a robust 2stage Class A/AB amplifier module for use in the driver stages of cellular base station power amplifiers. The power transistors are fabricated using Sirenza's latest, high performance LDMOS process. It is a drop-in, no-tune, solution for high power applications requiring high efficiency, excellent linearity, and unit-to-unit repeatability. This unit operates from a single voltage supply and has internal temperature compensation of the bias voltage to ensure stable performance over the full temperature range. It is internally matched to 50 ohms.
XD010-12S-D4F
869-894 MHz Class AB 15W Power Amplifier Module
Functional Block Diagram
Stage 1 Stage 2
Product Features
Bias Network
Temperature Compensation
* * * * * * *
4
50 W RF impedance 15W Output P1dB Single Supply Operation : Nominally 28V High Gain: 32 dB at 880 MHz Robust 8000V ESD (HBM), Class 3B XeMOS II LDMOS FETS Temperature Compensation
Applications
1
2
3
RF in
VD1
VD2 Case Flange = Ground
RF out
* * * *
Base Station PA driver Repeater CDMA / WCDMA GSM / EDGE
Key Specifications
Symbol Frequency P1dB Gain Gain Flatness IRL Efficiency Parameter Frequency of Operation Output Power at 1dB Compression, 880MHz Gain at 1W Output Power, 880MHz Peak to Peak Gain Variation, 869 - 894MHz Input Return Loss 1W Output Power, 869 - 894MHz Drain Efficiency at 12W CW, 880MHz Drain Efficiency at 2W CDMA (Single Carrier IS-95) Drain Efficiency at 1W CDMA (Single Carrier IS-95) ACPR at 2W CDMA (Single Carrier IS-95, 9 Ch Fwd, Offset=750KHz, ACPR Integrated Bandwidth), 880MHz Linearity ALT-1 at 2W CDMA (Single Carrier IS-95, 9 Ch Fwd, Offset=1980KHz, ACPR Integrated Bandwidth), 880MHz 3 Order IMD at 12W PEP (Two Tone), 880MHz 3rd Order IMD at 1W PEP (Two Tone), 880MHz Delay Phase Linearity RTH, j-l RTH, j-2 Signal Delay from Pin 1 to Pin 4 Deviation from Linear Phase (Peak to Peak) Thermal Resistance Stage 1 (Junction to Case) Thermal Resistance Stage 2 (Junction to Case)
rd
Unit MHz W dB dB dB % % % dB dB dBc dBc nS Deg C/W C/W
Min. 869 12 30 14 27 -
Typ. 15 32 0.2 17 33 12 7 -51 -70 -36 -45 2.5 0.5 11 4
Max. 894 1.0 -32 -
Test Conditions Zin = Zout = 50, VD = 28.0V, IDQ1 = 230 mA, IDQ2 =150mA, TFlange = 25C
1625-1675The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC 1
http://www.sirenza.com EDS-102934 Rev C
XD010-12S-D4F 869-894 MHz 15W Power Amp Module
Quality Specifications
Parameter ESD Rating MTTF Human Body Model, JEDEC Document - JESD22-A114-B 85o C Leadframe, 200 C Channel
o
Unit V Hours
Typical 8000 1.2 X 106
Pin Description
Pin # 1 2 3 4 Flange Function RF Input VD1 VD2 RF Output Gnd Description Module RF input. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be taken to protect against video transients that may damage the active devices. This is the drain voltage for the first stage. Nominally +28Vdc This is the drain voltage for the 2nd stage of the amplifier module. The 2nd stage gate bias is temperature compensated to maintain constant quiscent drain current over the operating temperature range. See Note 1. Module RF output. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be taken to protect against video transients that may damage the active devices. Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for optimum thermal and RF performance. See mounting instructions in application note AN-060 on Sirenza's web site.
Simplified Device Schematic
2 VD1 3 VD2
Temperature Compensation Bias Network
RF in 1
Q1
Q2
RF out 4
Case Flange = Ground
Absolute Maximum Ratings
Parameters 1st Stage Bias Voltage (VD1 ) 2
nd
Value 35 35 +20 5:1 +200 -20 to +90 -40 to +100
Unit V V dBm VSWR C C C
Stage Bias Voltage (VD2)
RF Input Power Load Impedance for Continuous Operation Without Damage Output Device Channel Temperature Operating Temperature Range Storage Temperature Range
Note 1: The internally generated gate voltage is thermally compensated to maintain constant quiescent current over the temperature range listed in the data sheet. No compensation is provided for gain changes with temperature. This can only be accomplished with AGC external to the module. Note 2: Internal RF decoupling is included on all bias leads. No additional bypass elements are required, however some applications may require energy storage on the drain leads to accommodate time-varying waveforms. Note 3: This module was designed to have its leads hand soldered to an adjacent PCB. The maximum soldering iron tip temperature should not exceed 700 C, and the soldering iron tip should not be in direct contact with the lead for longer than 10 seconds. Refer to app note AN060 (www.sirenza.com) for further installation instructions.
Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation see typical setup values specified in the table on page one.
Caution: ESD Sensitive
Appropriate precaution in handling, packaging and testing devices must be observed.
303 S. Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC 2
http://www.sirenza.com EDS-102934 Rev C
XD010-12S-D4F 869-894 MHz 15W Power Amp Module
Typical Performance Curves
Gain, Efficiency, ACP, ALT1 vs. Output Power Freq=881 MHz, Vdd=28 V, TFlange=25 oC IS95 standard, channel BW= 1.23 MHz. ADJ BW= 30 KHz @ 750 KHz spacing. ALT1 BW= 30 KHz @ 1980 KHz spacing.
Gain, ACP vs. Output Power over Temperature Freq=881 MHz, Vdd=28 V, TFlange=-20 oC, 25 oC, 90 oC IS95 standard, channel BW= 1.23 MHz. ADJ BW= 30 KHz @ 750 KHz spacing. ALT1 BW= 30 KHz @ 1980 KHz spacing.
-10 -20 Gain Gain (dB), Efficiency (%) ACP (dB), ALT1 (dB) 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Efficiency ACP ALT1 -30 -40 -50 -60 -70 -80
10 0 0.5 1 1.5 2 2.5 3 3.5 4 -70 35 -20
35 30
30 Gain @ -20 Gain (dB) 25 Gain @ 90 ACP @ 25 20 Gain @ 25
-30
ACP @ 90 -50
15
-60
Output Power (W)
Output Power (W)
35 30 Gain (dB), Efficiency (%) 25 20 15 10 5 0 865
Gain, Efficiency, IRL, ACP, ALT1 vs. Frequency Output Power= 1 Watt Vdd=28 V, TFlange=25 oC IS95 standard, channel BW= 1.23 MHz. ADJ BW= 30 KHz @ 750 KHz spacing. ALT1 BW= 30 KHz @ 1980 KHz spacing.
Output Power, Gain, Efficiency vs. Input Power Freq=881 MHz, Vdd=28 V, TFlange=25oC
-10
40 Output Power (W), Gain (dB), Efficiency (%) 35 30 25 20 15 10 5 0 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009
-20 Gain Efficiency IRL ACP ALT1 -50 -60 -70 -80 900 -30 -40 IRL(dB), ACP(dB), ALT1(dB)
Output Power Gain Efficiency
870
875
880
885
890
895
Frequency (MHz)
Input Power (W)
303 S. Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC 3
http://www.sirenza.com EDS-102934 Rev C
ACP (dB)
ACP @ -20
-40
XD010-12S-D4F 869-894 MHz 15W Power Amp Module
Typical Performance Curves (cont'd)
Gain, Efficiency vs. Output Power over Temperature Freq=881 MHz, Vdd=28 V, TFlange=-20 oC, 25 oC, 90 oC
45 40
30 -14 -15 -16 -17 -18 -19 -20 900 35
Gain, Efficiency, IRL vs. Frequency Output Power=1 Watt, Vdd=28 V, TFlange=25 oC
-13
35 Gain (dB) ,Efficiency (%)
Gain (dB), Efficiency (%)
30 25 20 15 10 5 0 0 2 4 6 8 10 12 14 16 Gain, Temp= -20 Gain, Temp= 25 Gain, Temp= 90 Efficiency, Temp= -20 Efficiency, Temp= 25 Efficiency, Temp= 90
25 20 15 10 5 0 865
Gain Efficiency IRL
870
875
880
885
890
895
Output Power (W)
Frequency (MHz)
303 S. Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC 4
http://www.sirenza.com EDS-102934 Rev C
IRL (dB)
XD010-12S-D4F 869-894 MHz 15W Power Amp Module
Test Board Schematic with module connections shown Test Board Bill of Materials
Component PCB J1, J2 J3 C1, C10 C2, C20 C3, C30 C25, C26 C21, C22 C23, C24 Mounting Screws Description Rogers 4350, er=3.5 Thickness=30mils SMA, RF, Panel Mount Tab W / Flange MTA Post Header, 6 Pin, Rectangle, Polarized, Surface Mount Cap, 10mF, 35V, 10%, Tant, Elect, D Cap, 0.1mF, 100V, 10%, 1206 Cap, 1000pF, 100V, 10%, 1206 Cap, 68pF, 250V, 5%, 0603 Cap, 0.1mF, 100V, 10%, 0805 Cap, 1000pF, 100V, 10%, 0603 4-40 X 0.250" Manufacturer Rogers Johnson AMP Kemet Johanson Johanson ATC Panasonic AVX Various
Test Board Layout
To receive Gerber files, DXF drawings, a detailed BOM, and assembly recommendations for the test board with fixture, contact applications support at support@sirenza.com. Data sheet for evaluation circuit (XD010-EVAL) available from Sirenza website.
303 S. Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC 5
http://www.sirenza.com EDS-102934 Rev C
XD010-12S-D4F 869-894 MHz 15W Power Amp Module
Package Outline Drawing
Recommended PCB Cutout and Landing Pads for the D4F Package
Note 3: Dimensions are in inches
Refer to Application note AN-060 "Installation Instructions for XD Module Series" for additional mounting info. App note availbale at at www.sirenza.com
303 S. Technology Court Broomfield, CO 80021
Phone: (800) SMI-MMIC 6
http://www.sirenza.com EDS-102934 Rev C

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